The invention relates to a time-alignment apparatus for providing data frames of a plurality of channels with predetermined time-offsets. The time-alignment apparatus is provided in a transmitter of a telecommunication system and receives successive data frames, each containing a predetermined number of data symbols, respectively from a number of channels and outputs the data symbols successively with predetermined time-offsets relative to a common synchronization clock. The invention also relates to a method for performing such a time-alignment, a transmitter of a telecommunication system and a telecommunication system, in which such a time-alignment is performed in a transmitter.
Typically, the time-alignment apparatus and the method are used in a telecommunication system based on a time division multiplexing or CDMA transmission. In such systems, the time-offset relative to a common synchronization signal indicates the beginning of the radio frames of the corresponding channels on the radio link (air interface or antenna). Before the transmission onto the radio link, the individual data frames must be stored and must then be provided with the time-offset. The invention particularly relates to the problem of how the different time-offsets between the data frames of a great number of user channels can be handled, in particular for a CDMA telecommunication system.
In many telecommunication systems, the individual data frames of a number of channels are generated asynchronously, i.e. ATM data frames are not generated aligned to a given synchronization clock in the transmitter. If the individual channels have the same basic transmission rate TRB (on the air interface) the data frames will contain the same number of data symbols, however, they will still not be aligned to a common synchronization clock. The task of the transmitter is, despite the asynchronously arriving data packets from the individual channels, to transmit the data frames (or more precisely their data symbols) on the radio link with a predetermined respective time-offset per channel, which then characterizes the beginning of data frames of this particular user channel. The transmission to the receiver can introduce further time delays between the individual data frames, for example due to varying distances during the transmission, such that the receiver must perform a time-alignment with respect to a common synchronization clock provided in the receiver. The present invention relates to the time-offset adjustment in the transmitter.
An example of a mobile radio communication system, where such a time-offset adjustment is required, is a CDMA mobile radio communication system. FIG. 5 shows a block diagram of a base transceiver station BTS in such a CDMA communication system. FIG. 6 shows the encoder unit ENC of the base transmitter station BTS in FIG. 6. It should be noted that hereinafter the invention and their problems will be considered with respect to the CDMA system shown in FIGS. 5, 6, however, the time-alignment is also applicable to any communication system requiring a time-offset adjustment.
In all telecommunication systems, where several channels each comprising successive data frames are provided, a separate encoder dedicated to a specific user channel must be provided in order to encode the successively arriving data frames of one particular channel. However, this would result in e.g. up to 300 encoder units, which is unacceptable in terms of the required hardware effort. For this reason, there is always the problem of how a common encoder resource can be used efficiently for encoding the data frames of all channels. In principle, this can be achieved if the time, which the encoder spends on encoding one data frame is much shorter than the duration of the data frame itself. Then, the encoder can process the data frames of several channels one after the other within one data frame period. Since the data frames of the individual channels do not arrive synchronized to a common synchronization clock and must be provided with a predetermined time-offset per channel to the air interface, the arriving data frames must be buffered in a memory, before a predetermined time-offset can be applied to them such that the data symbols can be delivered in form of a constant stream of data symbols to the modulation unit (e.g. the CDMA modulator BBTX in FIG. 6).
The invention particularly relates to the problem of how different time-offsets c an be applied to the (possibly asynchronously) arriving data frames of a great number of channels.
As described above, due to the fact that the time-offsets indicate the beginning of the individual radio frames of the corresponding channel on the radio link, the encoder unit must ensure that the individually (possibly asynchronously) arriving data frames from the user channels are available with a unique time-offset on the radio link. In addition to the problem that the data frames have to be provided with unique time-offsets, often an interleaving of data frame, more precisely of the data symbols contained therein, must be performed, i.e. the data symbols should be rearranged (interleaved) before the data symbols are provided as a data symbol stream to the modulator. The time-offset provision is to achieve minimum interference between the individual channels, i.e. it shall improve the correlation properties of a CDMA receiver. An additional interleaving improves the data reception at the receiver in fading channel environments which introduce burst errors in the received data frames.
Therefore, the object of the invention is to provide a time-alignment apparatus, a transmitter of a telecommunication system, in particular an encoder unit of a CDMA-system, a telecommunication system and a time-alignment method, which enable user data arriving in data frames from a plurality of user channels to have individually assigned unique time-offsets before transmission into the air, such that the interference between the code channels, for example the CDMA channels in a CDMA system, is minimized.
Another object of the invention is to provide a time-alignment apparatus, a transmitter of a telecommunication system, a telecommunication system and a time-alignment method, with which the encoder hardware can be used efficiently even for a large number of user channels.
This object is solved by a time-alignment apparatus of a transmitter of a telecommunication system for receiving successive data frames, each containing a predetermined number of data symbols, respectively from a number of channels, and for successively outputting the data symbols with a predetermined time-offset relative to a common synchronization clock, comprising:
a) at least a first, second and third read/write frame memory, each having a number of storage resources each for storing the data symbols of one data frame of a respective channel, sa-id frame memories each having a write state in which data is written to said frame memories by an input means and a read state (in which data is read from said frame memories by an output means;
b) a control unit for cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronization clock such that
b1) in said first alignment mode said first and second frame memory are in a write state and said third frame memory is in a read state;
b2) in said second alignment mode said second and third frame memory are in a write state and said first frame memory is in a read state; and
b3) in said third alignment mode said third and first frame memory are in a write state and said second frame memory is in a read state;
c) a write/read address providing means for providing a respective frame start write address (corresponding to said time-offset individually for each storage resource of a frame memory having a write state, and successive read addresses commonly for all storage resources of a frame memory having a read state;
d) wherein after each mode switching the input means starts writing the data symbols of a newly arriving data frame of every channel into the respective storage resource of a first write state frame memory which was in a read state in the previous mode at the respective frame start write address, and continues writing the data symbols into a corresponding storage resource of the other second frame memory having a write state at a write base address, if during the writing of the data symbols in said first frame memory the highest possible write address of the respective storage resource is reached; and
e) wherein said output means successively reads one data symbol from the respective storage resources of said frame memory having a read state (at said successive read addresses.
Furthermore, the object is solved by a time-alignment apparatus of a transmitter of a telecommunication system for receiving successive data frames, each containing a predetermined number of data symbols, respectively from a number of channels, and for successively outputting the data symbols with a predetermined time-offset relative to a common synchronization clock, comprising:
a) at least a first, second and third read/write frame memory, each having a number of storage resources each for storing the data symbols of one data frame of a respective channel, said frame memories each having a write state in which data is written to said frame memories by an input means and a read state in which data is read from said frame memories by an output means;
b) a control unit for cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronization clock such that
b1) in said first alignment mode said first and second frame memory are in a read state and said third frame memory is in a write state;
b2) in said second alignment mode said second and third frame memory are in a read state and said first frame memory is in a write state; and
b3) in said third alignment mode said third and first frame memory (are in a read state and said second frame memory is in a write state;
c) a write/read address providing means for providing a respective frame start read address corresponding to said time-offset individually for each storage resource of a frame memory having a read state, and successive write addresses commonly for all storage resources of the frame memory having a write state;
d) wherein after each mode switching the input means successively writes the data symbols of a newly arriving data frame of every channel into the respective storage resource of the frame memory having a write state at said successive write addresses; and
e) wherein said output means reads one data symbol from the respective storage resources of a first frame memory which was in a write state in the previous mode at the respective frame start read address, and continues reading the data symbols from a corresponding storage resource of the other second frame memory having a read state at a read base address, if during the reading of the data symbols in said first frame memory the highest possible read address of the respective storage resource is reached.
Furthermore this object is solved by a transmitter of a telecommunication system comprising a time-alignment apparatus as defined above.
The object is also solved by a telecommunication system comprising one or more transmitters as defined above.
Furthermore, the object is also solved by a method for time-aligning successive data frames each containing a predetermined number of data symbols number of channels, and for successively outputting the data symbols with a predetermined time-offset relative to a common synchronization clock, comprising the following steps:
a) writing data frames into at least a first, second and third read/write frame memory each having a number of storage resources each for storing the data symbols of one data frame of a respective channel, said frame memories each having a write state in which data is written to said frame memories by an input means and a read state in which data is read from said frame memories by an output means;
b) cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronization clock wherein
b1) in said first alignment mode said first and second frame memory are in a write state and said third frame memory is in a read state;
b2) in said second alignment mode said second and third frame memory are in a write state (WR) and said first frame memory is in a read state; and
b3) in said third alignment mode said third and first frame memory are in a write state (WR) and said second frame memory is in a read state;
c) providing a respective frame start write address corresponding to said time-offset selectively for each storage resource of a frame memory having a write state, and successive read addresses commonly for all storage resources of a frame memory having a read state;
d) writing, after each mode switching the data symbols of a newly arriving data frame of every channel into the respective storage resource of a first write state frame memory which was in a read state in the previous mode at the respective frame start write address, and continuing said writing of the data symbols into a corresponding storage resource of the other second frame memory having a write state a write base address, if during the writing of the data symbols in said first frame memory the highest possible write address of the respective storage resource is reached; and
e) successively reading one data symbol from the respective storage resources of said frame memory having a read state at said successive read addresses.
Furthermore, the object is also solved by a method for time-aligning successive data frames; each containing a predetermined number of data symbols, respectively from a number of channels, and for successively outputting the data symbols with a predetermined time-offset and for successively outputting the data symbols with a predetermined time-offset relative to a common synchronization clock, comprising the following steps:
a) writing data frames into at least a first, second and third read/write frame memory, each having a number of storage resources each for storing the data symbols of one data frame of a respective channel, said frame memories each having a write state in which data is written to said frame memories by an input means and a read state in which data is read from said frame memories by an output means;
b) cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronization clock such that
b1) in said first alignment mode said first and second frame memory are in a read state and said third frame memory is in a write state;
b2) in said second alignment mode said second and third frame-memory are in a read state and said first frame memory is in a write state; and
b3) in said third alignment mode said third and first frame memory are in a read state and said second frame memory (RAM2) is in a write state;
c) providing a respective frame start read address corresponding to said time-offset selectively for each storage resource of a frame memory having a read state, and successive write addresses commonly for all storage resources of the frame memory having a write state;
d) successively writing after each mode switching the data symbols of a newly arriving data frame of every channel into the respective storage resource of the frame memory having a write state at said successive write addresses; and
e) reading one data symbol from the respective storage resources of a first frame memory which was in a write state in the previous mode at the respective frame start read address, and continuing the reading of the data symbols from a corresponding storage resource of the other second frame memory having a read state at a read base address, if during the reading of the data symbols in said first frame memory the highest possible read address of the respective storage resource is reached.
The object of the invention is also solved by claims 9, 13, 14, 15, 16, 17, 18, 19, 20.
According to a first aspect of the present invention (logically) three frame memories are used. Each frame memory can hold one complete data frame of all channels. During one period of an external common synchronization clock, two memories are used to write data frames and an one is used to read data. Of course, as a practical embodiment of the invention, either three single port RAMs (either used for reading or writing) or dual port RAMs (reading and writing at the same time) can be used. Thus, the three separate memories according to the invention should only be logically seen as three separate memories, whereas one memory in terms of dual port RAMs can be used.
The unique time-offset of the individual data frames is (physically) realized by performing a writing process to two of the three RAMs being in a write state simultaneously during one frame cycle. Whilst writing to two RAMs having a write state the individual user data with its respective time-offset, occurring as a shift of the data symbols for one data frame over two RAMs, the reading from the third RAM is performed. When the next common synchronization clock pulse (frame synchronization pulse) occurs, the function of the three RAMs is cyclically changed. That is, the RAM used for reading will then be used as a RAM for writing and one of the two RAMs previously being used for the writing is now used for the reading of the data. The time-offset between the data frames of the individual channels relative to the synchronization clock can be adjusted to vary between 0 and a complete frame period. When the desired time-offset is 0, only the first RAM will have any data entries for this specific channel during one writing period. For time-offsets between 0 and one complete data frame, the data frame is written into two write RAMs. If the maximum of the time-offset is one frame, then the data is stored only in the second RAM. For time-offsets between 0 and one frame arriving packets containing data for one frame can overlap only two RAMs at the most.
Three RAMs and the cyclical change of the functions of the three RAMs thus enable that data frames having individually unique time-offsets (within the range of one frame) can be stored and transmitted with the desired time-offset relative to one common frame synchronization pulse. It is important that after each cyclic change a newly arriving data frame of each channel is always written to the frame memory, which was in the read state in the previous mode. When the writing of the data frames is performed to the one or two write state frame memories, a write/read base address providing means provides a write base address corresponding to the time-offset. That is, if data frames arrive asynchronously at the encoder, the address providing means will issue the write base address at which the writing is to be started in the memory. Thus, the time-offset is realized by starting to write the data frames into the individual resources (=memory positions) of the frame memory at the given write base address.
A second aspect of the invention is to only use one frame memory for the writing and two frame memories for the reading. In this case, an arriving data frame is always written to the single write state memory at the lowest address and after the cyclic change performed with the occurrence of the next synchronization clock, the writing of data frames is continued in the next write state frame memory. In this case, the unique time-offset is realized by issuing predetermined read base addresses which indicate at which memory position the reading is to be started in the first read state memory.
In the above described aspects of the invention, data frames of the plurality of user channels are respectively written into a storage resource of the respective memory. One possibility is that each storage resource is realized by one row of the frame memory, wherein the output means reads the data symbols successively along the column direction at the given read base addresses. In this case, no bit-interleaving is performed.
On the other hand, in many communication systems, on the transmitter side, a bit-interleaving is desired as explained above. In this case, according to a third aspect of the invention to achieve the interleaving, the writing into a respective storage resource also starts at the respective write base address, but the data symbols are not written simply sequentially in a row direction one after the other. The writing order is changed dependent on the desired interleaving technique (e.g. interleaving depth) such that during the reading process from the memory having the read state the data symbols are provided in the same order as if they had been written to an interleaving matrix (e.g. of a specific interleaving depth) and were read out in the column direction therefrom.
According to a fourth aspect of the invention, the data symbols of the data frames may be individual bits and may be stored separately at each memory location of the individual frame memories. However, if for example the data has undergone an I/Q selection process for digital QPSK modulation then data symbols built of two or more bits may arrive serially or parallel at the time-alignment apparatus. According to another aspect of the invention, if the data symbols consist of two or more bits, the individual bits of the data symbols are stored together in one memory location. Namely, the bits are not stored bit by bit (as in the conventional art) but in fact in data symbols comprising two or more data bits.
Further advantageous embodiments and improvements of the invention can be taken from the following description and the dependent claims. Hereinafter, the invention will be explained with reference to its embodiments and with reference to the attached drawings.